IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 41

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Device-Level Description
Table 3–3. Datapath Interface
© March 2009 Altera Corporation
control_doing_wr
control_wdata_valid
control_dqs_burst
control_wdata[]
control_be[]
control_doing_rd
control_rdata[]
Signal name
In the write direction, the wdata_valid signal acts as an enable on the
local_wdata registers. The output of these registers is clocked into registers in the
IOE where it is fed to the DQ pins. The registers in the IOE are clocked by the write
clock (which is 90° before the system clock) so that DQS, which is generated by the
datapath, appears in the center of the data on the DQ pins. The write DQS is
generated from registers clocked by the system clock so that the t
at the DDR or DDR2 SDRAM device.
Table 3–3
shows the interface to the datapath.
Direction
Output
Input
Input
Input
Input
Input
Input
The control_doing_wr signal is asserted when the controller is
writing to the DDR or DDR2 SDRAM and controls the output enables on
the DQ pins.
The control_wdata_valid signal is a registered version of the
write data request to the local interface. It enables the write data and
byte enable registers so that they are only updated when valid data and
enables are available.
The control_dqs_burst signal controls the output enables of the
DQS pins. The DQS output enable must be asserted for longer than the
DQ output enable, particularly when the local burst size is shorter than
the memory burst length.
The control_wdata signal is the write data bus and should have
valid data in the same clock cycle that control_wdata_valid is
asserted.
The control_be signal is the byte enable bus and should have valid
data in the same clock cycle that control_wdata_valid is
asserted. The byte enables are converted into DDR or DDR2 SDRAM
data mask signals.
The control_doing_rd signal is asserted when the controller is
reading from the DDR or DDR2 SDRAM and enables the DQ capture
registers. It also controls the postamble control registers to prevent the
DQ capture registers from being inadvertently clocked after the DQS
read postamble.
The control_rdata bus is the read data bus and has valid data
some clock cycles after the read command is issued. The exact
relationship depends on the CAS latency of the memory and whether or
not registered DIMMs are being used.
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
DQSS
parameter is met
3–5