IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 15

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
SOPC Builder Design Flow
© March 2009 Altera Corporation
f
1
c
6. Turn on Advanced Mode, and click the Project Settings tab.
7. Ensure Update the example design file that instantiates the controller variation
Constraints
To choose the constraints for your device, follow these steps:
If you chose to target an Altera board, all the constraint settings are correct for that
board.
1. Click Step 2: Constraints.
2. Select the positions on the device for each of the DDR SDRAM byte groups. To
Add/Update Component
To add or update the component and generate the system, follow these steps:
1. Click Step 3: Add/Update Component, to add the custom variation to SOPC
2. SOPC Builder uses the module name (default ddr_sdram_0) for the variation
3. In SOPC Builder, create the rest of your SOPC Builder system.
4. Optional. Click the System Generation tab and turn on Simulation. Create
Only use these simulation model output files for simulation purposes and expressly
not for synthesis or any other purposes. Using these models for synthesis creates a
nonfunctional design.
For more information on the Nios II simulation flow, refer to
II Handbook.
5. On the System Generation tab, click Generate.
is turned on, so that the IP Toolbench automatically updates the example design
and the testbench.
place a byte group, select the byte group in the drop-down menu at your chosen
position.
1
1
Builder.
name of your DDR or DDR2 SDRAM Controller. You can change this name if you
want to.
project simulator files. to create simulation files for your project.
1
The floorplan matches the orientation of the Quartus II floorplanner. The
layout represents the die as viewed from above. A byte group consists of
four or eight DQ pins, a DM pin, and a DQS pin.
IP Toolbench chooses the correct positions, if you are using an Altera board
preset.
Before you click Generate, you must add at least one Avalon-MM master to
your system.
DDR and DDR2 SDRAM Controller Compiler User Guide
volume 4
of the Quartus
2–5