IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 29

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Table 2–2. Files to Compile—VHDL IP Functional Simulation Models
© March 2009 Altera Corporation
altera_mf
lpm
sgate
<device name>
altera
auk_ddr_user_lib
Notes to
(1) Fed-back clock mode only.
(2) Stratix series only.
Table
Library
2–2:
VHDL IP Functional Simulations
For VHDL simulations with IP functional simulation models, follow these steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool inside this directory and create the following
3. Compile the files in
libraries:
■
■
■
■
■
■
format.
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/220pack.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/220model.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/sgate_pack.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/sgate.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd
<QUARTUS ROOTDIR>/libraries/vhdl/altera/altera_europa_support_lib.vhd
<MegaCore install directory>/lib/auk_ddr_tb_functions.vhd
<project directory>/<variation name>_auk_ddr_dqs_group.vhd
<project directory>/<variation name>_auk_ddr_clk_gen.vhd
<project directory>/<variation name>_auk_ddr_datapath.vhd
<project directory>/<variation name>_auk_ddr_datapath_pack.vhd
<project directory>/<v>.vho
<MegaCore install directory>/lib/example_lfsr8.vhd
<project directory>/<variation name>_example_driver.vhd
<project directory>/ddr_pll_<device name>.vhd
<project directory>/ddr_pll_fb_<device name>.vhd
<project directory>/<variation name>_auk_ddr_dll.vhd
<project directory>/<project name>.vhd
<project directory>/testbench/<testbench name>.vhd
altera_mf
lpm
sgate
<device name>
altera
auk_ddr_user_lib
Table 2–2
into the appropriate library. The files are in VHDL93
Filename
DDR and DDR2 SDRAM Controller Compiler User Guide
(1)
(2)
2–19