IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 65

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Interfaces & Signals
Table 3–7. System Signals (Part 2 of 2)
Figure 3–19. Circuit for resynch_clk_edge_select
Table 3–8. Local Interface Signals (Part 1 of 2)
© March 2009 Altera Corporation
write_clk
dqs_ref_clk
fedback_clock_out
stratix_dll_control
Note to
(1) This signal only exists on the custom variation when a dedicated clock phase is required, otherwise the connection is made inside the custom
local_addr[]
local_be[]
local_burstbegin
local_read_req
local_refresh_req
variation.
Table
Signal Name
Register
Capture
Signal Name
3–7:
Table 3–8
Resynchronization
Register
Direction
shows the DDR and DDR2 SDRAM controller local interface signals.
Input
Input
Input
Input
Input
Direction
Output
Output
Output
Input
Memory address at which the burst should start. The width of this bus is sized
using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 1
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 1
The least significant bit (LSB) of the column address on the memory side is
ignored, because the local data width is twice that of the memory data bus
width.
The order of the address bits is set in the clear text part of the MegaCore
function (auk_ddr_sdram.vhd). The order is chips, bank, row, column, but
you can change it if required.
Byte enable signal, which you use to mask off individual bytes during writes.
Avalon-MM burst begin strobe, which indicates the beginning of an Avalon-
MM burst. This signal is only available when the local interface is an Avalon-
MM interface and the memory burst length is greater than 2.
Read request signal.
User controlled refresh request. If User Controlled Refresh is turned on,
local_refresh_req becomes available and you are responsible for
issuing sufficient refresh requests to meet the memory requirements. This
option allows complete control over when refreshes are issued to the memory
including ganging together multiple refresh commands. Refresh requests take
priority over read and write requests unless they are already being processed.
Resynchronization
Shifted clock that center aligns write data to the memory.
Stratix DLL reference clock output.
Fed-back clock output.
Disables the Stratix DLL reference clock during reads.
Register
Extra
DDR and DDR2 SDRAM Controller Compiler User Guide
Multiplex
Description
Description
Register
Pipeline
local_rdata
3–29