IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 22

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–12
DDR and DDR2 SDRAM Controller Compiler User Guide
f
f
5. Click the Controller tab.
6. Select Native or Avalon Memory-Mapped local interface. The Avalon-MM
7. Turn on the relevant clocking options.
8. Select your memory initialization options.
9. Select your memory controller options.
10. Turn on the relevant DLL reference clock options.
11. Click the Controller Timings tab.
12. Enter your memory timing parameters in the Required column, so that the
13. Click Memory Timings tab.
For more information on memory timings, refer to
14. If you chose Custom memory device, enter the device settings from your chosen
15. Click the Board Timings tab.
For more information on board timings, refer to
16. Turn on Manual pin load control, if you want to enter the pin loading for the
1
f
f
interface allows you to easily connect to other Avalon-MM peripherals.
f
f
controller timings meet the requirements specified on your memory’s datasheet.
The wizard picks the appropriate number of clock cycles between commands that
are needed and calculates the resulting delay in the Actual column.
1
memory’s datasheet, otherwise your chosen memory type device settings are
entered automatically.
FPGA pins.
Select Unbuffered memory if you are using unbuffered modules or
devices.
To manually enter the number of clock cycles, turn on Manually choose
clock cycles and enter values in the Cycles column.
For more information on memory parameters, refer to
page
For more information on controller parameters, refer to
page
For more information on the Avalon-MM interface, refer to the
Interface
For more information on controller timings, refer to
on page
3–32.
3–33.
Specifications.
3–37.
“Board Timings” on page
“Memory Timings” on page
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation
“Controller Timings”
Chapter 2: Getting Started
“Memory” on
“Controller ” on
3–39.
Avalon
3–38.