IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 81

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameters
Table A–2. Postamble Options (Part 2 of 2)
Table A–3. Capture Options
© March 2009 Altera Corporation
Postamble clock setting
Dedicated clock phase
Number of DQS delay
matching buffers
Manual capture control
Capture setting
Dedicated clock phase
Parameter
Parameter
Table A–3
0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
0 to 359
0 to 8
On or off
0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
0 to 359
shows the capture options (non-DQS mode only).
Range
Range
Selects which clock to use for the postamble logic: the
system clock, the write clock (a 90° advanced version of the
system clock), or a dedicated postamble clock. Also defines
which edge of the chosen clock to use for the postamble
logic. If you select falling edge, the data path automatically
inserts inverters on the clock inputs to the postamble control
registers.
Allows you to enter the phase of the dedicated postamble
clock that is used for timing analysis. IP Toolbench uses this
value to set up the PLL phase shift.
Inserts the chosen number of delay buffers on the undelayed
DQS in Stratix devices. Insert delay buffers when you are
using low frequencies, to ensure that the capture registers
are not disabled too early.
Turn on to specify the details of the clock used for the
capture logic. Otherwise, the details are calculated
automatically based on system timing,
page
Selects which clock to use for the capture logic: the system
clock, the write clock (a 90° advanced version of the system
clock), or a dedicated capture clock. Also defines which edge
of the chosen clock to use for the capture logic. If you select
falling edge, the data path automatically inserts inverters on
the clock inputs to the capture registers.
Allows you to enter the phase of the dedicated capture clock
that is used for timing analysis. IP Toolbench uses this value
to set up the PLL phase shift.
A–10.
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
Description
“DQS Postamble” on
A–3