IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 91

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Examples
Figure A–10. Inserting an Intermediate Postamble Register
Examples
© March 2009 Altera Corporation
Clock Input
Fedback
dqs
dq
Example A–1
following options:
■
■
■
■
■
Example A–1. System PLL and Clock Outputs
ddr_pll_stratixii g_stratixpll_ddr_pll_inst
Example A–2. Fedback PLL and Clock Outputs
ddr_pll_fb_stratixii g_stratixpll_ddr_fedback_pll_inst
Fedback
Use fedback clock = On
Manual resynchronization control = On
Resynchronization clock setting = Dedicated
Manual postamble control = On
Postamble clock setting = Dedicated
PLL
(
);
(
);
.c0 (clk),
.c1 (write_clk),
.c2 (dedicated_resynch_or_capture_clk),
.inclk0 (clock_source)
.c0 (fedback_resynch_clk),
.c1 (dedicated_postamble_clk),
.inclk0 (fedback_clk_in)
dq_capture
Q
D
and
D
Q
Example A–2
resynched_data
D
fedback_resynched_data
Q
Q
resynch_clk
show the generated PLLs and the PLL outputs for the
System
D
D
PLL
Q
inter_rdata
clk
postamble_clk
D
Q
DDR and DDR2 SDRAM Controller Compiler User Guide
Q
D
inter_rdata
D
Present when
Intermediate Postamble
Register is On
Q
A–13