IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 7

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This Compiler
General Description
Figure 1–1. DDR & DDR2 SDRAM Controller System-Level Diagram
Note to
(1) Optional, for Stratix series and HardCopy II devices only.
March 2009 Altera Corporation
Figure
Pass or Fail
1–1:
The DDR SDRAM Controller is optimized for Altera Stratix and Cyclone series; the
DDR2 SDRAM Controller is optimized for Altera Stratix II and Cyclone II devices
only. The advanced features available in these devices allow you to interface directly
to DDR or DDR2 SDRAM devices and to use the DQS signal in the read and write
direction.
Figure 1–1
or DDR2 SDRAM Controller MegaCore functions create for you.
Whether you use IP Toolbench in SOPC Builder or in the Quartus II software, it
generates example design, instantiates a phase-locked loop (PLL), an example driver,
your DDR or DDR2 SDRAM controller custom variation, and an optional DLL (for
Stratix series only). The example design is a fully-functional design that can be
simulated, synthesized, and used in hardware. The example driver is a self-test
module that issues read and write commands to the controller and checks the read
data to produce the pass/fail and test complete signals.
You can replace the DDR or DDR2 SDRAM controller encrypted control logic in the
example design with your own custom logic, which allows you to use the Altera
clear-text datapath with your own control logic.
The DDR and DDR2 SDRAM Controllers are very similar. The following differences
exist:
■
■
Initialization timing (refer to
and
CAS latency options:
■
■
Example Design
Example Driver
2.0, 2.5, or 3.0, for DDR SDRAM
3, 4, or 5, for DDR2 SDRAM
“DDR2 SDRAM Initialization Timing” on page
shows a system-level diagram including the example design that the DDR
DLL ( 1 )
PLL
Interface
Local
DDR SDRAM Controller
“DDR SDRAM Initialization Timing” on page 3–25
(Encrypted)
(Clear Text)
Data Path
Control
Logic
DDR and DDR2 SDRAM Controller Compiler User Guide
DDR SDRAM
3–26)
Interface
DDR SDRAM
1–3