IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 79

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameters
Table A–1. Resynchronization Options (Part 1 of 2)
© March 2009 Altera Corporation
Reclock resynchronized data
to the positive edge
Manual resynchronization
control
Resynchronize captured read
data in cycle
Resynchronization clock
setting
Parameter
Table A–1
For more information on the resynchronization options, refer to
on page
Automatic, Always, or Never When this option is set to “Always” the wizard inserts a set
On or off
0 to 6
0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
A–4).
shows the resynchronization options.
Range
of positive edge system clock registers in the read data path
and delays the read data valid signal appropriately. The extra
registers are useful if you are resynchronizing with a phase
other than the positive edge of the system clock, but at the
expense of a clock cycle of latency. Choosing Never
produces lower latency. However, it is then your
responsibility to reclock the read data to the positive edge of
the system clock. When this option is set to Automatic, the
wizard decides whether or not to insert the extra set of
registers based on the choice of resynchronization edge and
system clock.
When the resynchronization clock phase is close to the
positive edge of the system clock, this option inserts an
additional set of registers, clocked on the negative edge of
system clock, between the resynchronization clock domain
and the system clock domain.
Turn on to specify the details of the resynchronization clock.
Otherwise, the details are calculated automatically based on
system timing. You must turn on this option when you turn
on the DQS mode and the fedback PLL options.
The number of cycles of delay to allow for the round trip
delay.
Defines which clock to use for resynchronization: the system
clock, the write clock (a 90° advanced version of the system
clock), or a dedicated resynchronization clock. Also defines
which edge of the chosen clock to use to resynchronize the
captured data. If you select falling edge, the data path
automatically inserts inverters on the clock inputs to the
resynchronization registers.
When the resynchronization clock is set to either the system
clock or the write clock, you cannot alter the phase of the
resynchronization clock. To alter the resynchronization phase
clock, select the resynchronization clock as dedicated and
set the required phase.
A. Manual Timing Settings
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
“Resynchronization”