IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 58

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–22
Figure 3–14. Reads
Notes to
(1) The local_cs_addr, local_row_addr, local_bank_addr, and local_col_addr signals are a representation of the
(2) DDR Command shows the command that the command signals are issuing.
DDR and DDR2 SDRAM Controller Compiler User Guide
local_addr signal.
Figure
local_bank_addr
Local Interface
DDR Command ( 2 )
3–14:
local_row_addr
DDR SDRAM
local_col_addr
local_cs_addr
local_rdata_valid
local_write_req
local_read_req
Interface
local_ready
local_rdata
ddr_cas_n
ddr_ras_n
local_size
ddr_we_n
ddr_cs_n
ddr_cke
ddr_dqs
ddr_dm
ddr_ba
ddr_dq
1. The user logic requests the first read by asserting the local_read_req signal,
2. The user logic requests a second read to a different address, this time of size 2 (4
3. The user logic requests a third read to a different address, this time of size 1 (2 on
ddr_a
( 1 )
( 1 )
( 1 )
( 1 )
clk
and the size and address for this read. In this example, the request is a burst of
length 4 (8 on the DDR SDRAM side). The local_ready signal is asserted, which
indicates that the controller has accepted this request, and the user logic can
request another read or write in the following clock cycle. If the local_ready
signal was not asserted, the user logic must keep the read request, size, and
address signals asserted.
on the DDR SDRAM side). The local_ready signal remains asserted, which
indicates that the controller has accepted the request.
the DDR SDRAM side). The local_ready signal remains asserted, which
indicates that the controller has accepted the request.
0
0
0
170
050 055 057
4
1
1
2
040
040
1
1
NOP
000
[1]
057
F
0
1
[2]
0 0
[3]
ACT
170 000 0A0
E
1
NOP
F
0
RD
E
1
1
NOP
000
F
F
ACT
040 000 0AA
0
D
000
000
NOP
0
F
5348
RD
D
86F4 D310
NOP
F
000
0
BT RD BT
[4]
0AE
0AE
D
D
77F4
BT
Chapter 3: Functional Description
© March 2009 Altera Corporation
0479
000
NOP
54B0
54B0
F
CB48
Interfaces & Signals
[5]