IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 28

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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DDR and DDR2 SDRAM Controller Compiler User Guide
1
2. For VHDL, edit generic_ddr_sdram.vhd to instantiate your memory model (the
3. Start the ModelSim-Altera simulator.
4. Change your working directory to your IP Toolbench-generated file directory
5. Type the following command:
6. To simulate with an IP functional simulation model simulation, type the following
7. For a gate-level timing simulation (VHDL or Verilog HDL ModelSim output from
Simulating With Other Simulators
The IP Toollbench-generated Tcl script is for the ModelSim simulator only. If you
prefer to use a different simulation tool, follow these instructions. You can also use
the generated script as a guide. You also need to download and compile an
appropriate memory model.
The following variables apply in this section:
file already contains three example Micron memory model instantiations).
or
For Verilog HDL, edit the memory instantiations in the testbench to match your
memory model.
<directory name>\testbench\modelsim.
set memory_model <model_name>r
where <model_name> is the filename of the downloaded memory model.
command:
source <variation name>_ddr_sdram_vsim.tclr
the Quartus II software), type the following commands:
set use_gate_model 1r
source <variation name>_ddr_sdram_vsim.tclr
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<QUARTUS ROOTDIR> is the Quartus II installation directory
<simulator name> is the name of your simulation tool
<device name> is the Altera device family name
<project name> is the name of your Quartus II top-level entity or module.
<testbench name> is the name of your testbench entity or module
<MegaCore install directory> is the DDR and DDR2 SDRAM Controller
installation directory
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation
Chapter 2: Getting Started