IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 12

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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DDR & DDR2 SDRAM Controller Walkthrough
DDR and DDR2 SDRAM Controller Compiler User Guide
f
The DDR and DDR2 SDRAM Controller Compiler with SOPC Builder flow option
allows you to build a complete DDR or DDR2 SDRAM system. The DDR and DDR2
SDRAM Controller Compiler with SOPC Builder flow connects the DDR or DDR2
SDRAM Controller to the Avalon-MM interface, which allows you to easily create any
system that includes one or more of the Avalon-MM peripherals.
You specify system components and choose system options from a rich set of features,
and the SOPC Builder automatically generates the interconnect logic and simulation
environment. Thus, you define and generate a complete system in dramatically less
time than manual-integration methods.
To perform burst transactions when the DDR or DDR2 SDRAM controller is
instantiated in SOPC builder, you need another master such as a DMA controller to
initiate the burst transactions.
The performance of the entire system and in general the DDR or DDR2 SDRAM
controller depends upon the number of masters and slaves connected to the
Avalon-MM interface, which degrades as the number of masters and slaves connected
to it increases. If the number of masters connected to the slave increases, the size of the
arbiter (which is part of the Avalon-MM interface) increases, which reduces the
performance of the system. The DDR or DDR2 SDRAM controller performance is
limited by the frequency of Avalon-MM interface.
There is no latency associated within the Avalon-MM interface, when it transfers the
read or write request to the controller local interface. If there are multiple masters
connected to the DDR or DDR2 SDRAM controller, there may be wait states before
the request from the master is accepted by the controller.
This walkthrough explains how to create a custom variation of the DDR or DDR2
SDRAM Controller MegaCore function in a SOPC Builder system using the Altera
DDR SDRAM controller IP Toolbench and the Quartus II software.
As you go through the wizard, each step is described in detail. The flow used in this
SOPC Builder walkthrough ensures that the PLL is properly connected to the DDR or
DDR2 SDRAM controller and that the wizard-generated constraints are correctly
applied.
For more information on SOPC Builder, refer to
This walkthrough involves the following steps:
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“Create a New Quartus II Project” on page 2–3
“Launch SOPC Builder & IP Toolbench” on page 2–4
“Parameterize” on page 2–4
“Constraints” on page 2–5
“Add/Update Component” on page 2–5
volume 4
of the Quartus II Handbook.
© March 2009 Altera Corporation
Chapter 2: Getting Started
SOPC Builder Design Flow