UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 916

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) Synchronizing data bit
• The receiving node establishes synchronization by a level change on the bus because it does not have a sync
• The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
(a) Hardware synchronization
signal.
This synchronization is established when the receiving node detects the start of frame in the interframe space.
• When a falling edge is detected on the bus, that TQ means the sync segment and the next segment is the
Figure 20-20. Hardware Synchronization Due to Dominant Level Detection During Bus Idle
CAN bus
Bit timing
prop segment. In this case, synchronization is established regardless of SJW.
Interframe space
Sync
segment
Prop
segment
Start of frame
Phase
segment 1
CHAPTER 20 CAN CONTROLLER
Phase
segment 2
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