UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 97

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Accessing specific on-chip peripheral I/O registers
16-bit timer/event counter AA (TAA)
(n = 0 to 5, m = 0 to 3, 5)
16-bit timer/event counter AB (TAB)
(n = 0, 1)
Motor control
TMT
Watchdog timer 2 (WDT2)
Real-time output function (RTO)
A/D converter
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an
access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a
possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction
but enters the wait status. If this wait status occurs, the number of clocks required to execute an instruction
increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the
wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this
time are shown below.
Peripheral Function
TAAnCNT
TAAnCCR0, TAAnCCR1
TAAmIOC4
TABnCNT
TABnCCR0 to TABnCCR3
TABnIOC4
TAB0OPT1
TAB0DTC
TT0CNT
TT0TCR0, TT0TCR1
WDTM2
RTBL0, RTBH0
ADA0M0
ADA0CR0 to ADA0CR11
ADA0CR0H to ADA0CR11H
Register Name
Read
Write
Read
Write
Read
Read
Write
Read
Write
Read
Write
Write
Read
Write
Read
Write
(when WDT2 operating)
Write
(RTPC0.RTPOE0 bit = 0)
Read
Read
Read
Access
CHAPTER 3 CPU FUNCTION
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
3
1
1 or 2
1 or 2
1 or 2
k
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