UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1322

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped and
Item
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator (f
PLL
CPU
DMA controller
Interrupt controller
Timer
Real-time counter (RTC)
Watchdog timer (WDT2)
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
CAN
USB function
Note 5
2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced
3. If the STOP mode is set while the D/A converter is operating, the D/A converter is automatically stopped and
4. Even if the STOP mode is set while the D/A converter is operating, the power consumption is reduced
5.
starts operating again after the STOP mode is released. However, in that case, the A/D conversion results
after the STOP mode is released are invalid. All the A/D conversion results before the STOP mode is set are
invalid.
equivalently to when the A/D converter is stopped before the STOP mode is set.
the pin status becomes high impedance. After the STOP mode is released, D/A conversion resumes, the
setting time elapses, and the status returns to the output level before the STOP mode was set.
equivalently to when the D/A converter is stopped before the STOP mode is set.
μ
PD70F3770, 70F3771 only
TAA0 to TAA5
TAB0, TAB1
TMM0 to TMM3
TMT0
CSIF0 to CSIF4
I
UARTC0 to UARTC4
R
Setting of STOP Mode
2
)
C00 to I
XT
X
)
)
2
C02
Table 25-9. Operating Status in STOP Mode
Stops oscillation
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable when f
count clock
Stops operation
Stops operation
Operable when f
clock
Operable when the SCKFn input clock is selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected)
Stops operation (conversion result undefined)
Stops operation
Stops operation (output held)
Operable
Stops operation
See CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before STOP mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
Stops operation
Stops operation
When Subclock Is Not Used
Notes 3, 4
R
R
/8 is selected as the
is selected as the count
−
(high impedance is output)
Operating Status
CHAPTER 25 STANDBY FUNCTION
Oscillation enabled
Operable when f
the count clock
Operable when f
count clock
Operable when f
count clock
Notes 1, 2
When Subclock Is Used
R
XT
R
/8 or f
or f
is selected as the
XT
XT
is selected as the
Page 1322 of 1509
is selected as