UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1119
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(34) UF0 mode status register (UF0MODS)
UF0MODS
Bit position
This register indicates the configuration status.
This register is read-only, in 8-bit units.
6
4
3
2
7
0
CDCGD
MPACK
DFLT
CONF
Bit name
CDCGD
6
This bit specifies whether CPUDEC processing is performed for the GET_DESCRIPTOR
Configuration request.
This bit indicates the transmit packet size of Endpoint0.
This bit is automatically set to 1 by hardware after the GET_DESCRIPTOR Device
request has been processed (on normal completion of the status stage). It is not cleared
to 0 until the USBF has been reset (it is not cleared to 0 by Bus Reset).
If this bit is not set to 1, the hardware transfers only the automatically-executed request in
8-byte units. Therefore, even if data of more than 8 bytes is sent by the OUT token to be
processed by FW before completion of the GET_DESCRIPTOR Device request, the data
is correctly received.
This bit is ignored if the size of Endpoint0 is 8 bytes.
This bit indicates the default status (DFLT bit = 1).
This bit is automatically set to 1 by Bus Reset. The transaction for all the endpoints is not
responded to until this bit is set to 1.
This bit indicates whether the SET_CONFIGURATION request has been completed.
This bit is set to 1 when Configuration value = 1 is received by the
SET_CONFIGURATION request.
Unless this bit is set to 1, access to an endpoint other than Endpoint0 is ignored.
This bit is cleared to 0 when Configuration value = 0 is received by the
SET_CONFIGURATION request. It is also cleared to 0 when Bus Reset is detected.
5
0
1: Forcibly change the GET_DESCRIPTOR Configuration request to CPUDEC
0: Automatically process the GET_DESCRIPTOR Configuration request (default
1: Transmit a packet of other than 8 bytes.
0: Transmit a packet of 8 bytes (default value).
1: Enables response.
0: Disables response (always no response) (default value).
1: SET_CONFIGURATION request has been completed.
0: SET_CONFIGURATION request has not been completed (default value).
processing.
value).
MPACK
4
DFLT
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
CONF
2
Function
1
0
0
0
00200078H
Address
Page 1119 of 1509
After reset
00H
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