UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 770
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
CFnTMS
Note These bits can only be rewritten when the CFnPWR bit = 0. However, the CFnPWR
CFnDIR
[In single transfer mode]
[In continuous transfer mode]
The reception completion interrupt (INTCFnR) occurs when communication is
complete.
Even if transmission is enabled (CFnTXE bit = 1), the transmission enable interrupt
If the next transmit data is written during communication (CFnSTR.CFnTSF bit =
1), it is ignored and the next communication is not started. Also, if reception-only
communication is set (CFnTXE bit = 0, CFnRXE bit = 1), the next communication
is not started even if the receive data is read during communication (CFnSTR.
CFnTSF bit = 1).
The continuous transmission is enabled by writing the next transmit data during
communication (CFnSTR.CFnTSF bit = 1).
Writing the next transmission data is enabled after a transmission enable interrupt
(INTCFnT) occurs.
If reception-only communication is set (CFnTXE bit = 0, CFnRXE bit = 1) in the
continuous transfer mode, the next reception is started immediately after a
reception completion interrupt (INTCFnR), regardless of the read operation of the
CFnRX register.
Therefore, immediately read the receive data from the CFnRX register. If this read
operation is delayed, an overrun error (CFnOVE bit = 1) occurs.
(INTCFnT) does not occur.
0
1
0
1
Note
Note
can be set to 1 at the same time as these bits are rewritten.
Single transfer mode
Continuous transfer mode
MSB-first transfer
LSB-first transfer
Specification of transfer direction mode (MSB/LSB)
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Transfer mode specification
Page 770 of 1509
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