UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 9

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 177
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 200
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA).............................................................. 213
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.1
6.2
6.3
6.4
6.5
7.1
7.2
7.3
7.4
7.5
4.5.1 Cautions on setting port pins.........................................................................................................172
4.5.2 Cautions on bit manipulation instruction for port n register (Pn)....................................................175
4.5.3 Cautions on on-chip debug pins (V850ES/JG3-H only) ................................................................176
4.5.4 Cautions on P56/INTP05/DRST pin..............................................................................................176
4.5.5 Cautions on P10, P11, and P53 pins when power is turned on ....................................................176
4.5.6 Hysteresis characteristics .............................................................................................................176
Features .................................................................................................................................. 177
Bus Control Pins .................................................................................................................... 178
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ....................179
5.2.2 Pin status in each operation mode................................................................................................179
Memory Block Function ........................................................................................................ 180
Bus Access ............................................................................................................................. 181
5.4.1 Number of clocks for access .........................................................................................................181
5.4.2 Bus size setting function ...............................................................................................................181
5.4.3 Access by bus size .......................................................................................................................182
Wait Function.......................................................................................................................... 189
5.5.1 Programmable wait function..........................................................................................................189
5.5.2 External wait function....................................................................................................................190
5.5.3 Relationship between programmable wait and external wait.........................................................191
5.5.4 Programmable address wait function ............................................................................................192
Idle State Insertion Function................................................................................................. 193
Bus Hold Function (V850ES/JH3-H only)............................................................................. 194
5.7.1 Functional outline..........................................................................................................................194
5.7.2 Bus hold procedure.......................................................................................................................195
5.7.3 Operation in power save mode .....................................................................................................195
Bus Priority ............................................................................................................................. 196
Bus Timing.............................................................................................................................. 197
Overview ................................................................................................................................. 200
Configuration.......................................................................................................................... 201
Registers ................................................................................................................................. 203
Operation ................................................................................................................................ 208
6.4.1 Operation of each clock ................................................................................................................208
6.4.2 Clock output function ....................................................................................................................208
PLL Function .......................................................................................................................... 209
6.5.1 Overview .......................................................................................................................................209
6.5.2 Registers.......................................................................................................................................209
6.5.3 Usage ...........................................................................................................................................212
Overview ................................................................................................................................. 213
Functions ................................................................................................................................ 213
Configuration.......................................................................................................................... 214
7.3.1 Pin configuration ...........................................................................................................................216
Registers ................................................................................................................................. 217
Operation ................................................................................................................................ 234
7.5.1 Interval timer mode (TAAmMD2 to TAAmMD0 bits = 000) ...........................................................240
7.5.2 External event count mode (TAAnMD2 to TAAnMD0 bits = 001)..................................................250
7.5.3 External trigger pulse output mode (TAAnMD2 to TAAnMD0 bits = 010) .....................................258
7.5.4 One-shot pulse output mode (TAAnMD2 to TAAnMD0 bits = 011) ...............................................270
7.5.5 PWM output mode (TAAnMD2 to TAAnMD0 bits = 100) ..............................................................277
7.5.6 Free-running timer mode (TAAnMD2 to TAAnMD0 bits = 101).....................................................286
7.5.7 Pulse width measurement mode (TAAnMD2 to TAAnMD0 bits = 110) .........................................303