UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 905
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
20.2.5 Overload frame
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
An overload frame is transmitted under the following conditions.
• When the receiving node has not completed the reception operation
• If a dominant level is detected at the first two bits during intermission
• If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error
delimiter/overload delimiter
Note In this CAN controller, all reception frames can be loaded without outputting an overload frame because of the
Remark
<1>
<2>
<3>
<4>
<5>
No
enough high-speed internal processing.
Overload flag
Overload flag from other node
Overload delimiter
Frame
Interframe space/overload
frame
D: Dominant = 0
R: Recessive = 1
Node n ≠ node m
R
D
(<4>)
Name
Table 20-8. Definition of Overload Frame Fields
6 bits
<1>
Overload frame
Figure 20-16. Overload Frame
0 to 6 bits
6
0 to 6
8
Bit Count
<2>
–
–
Outputs 6 dominant-level bits consecutively.
The node that received an overload flag in the interframe space
outputs an overload flag.
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame
is transmitted from the next bit.
Output following an end of frame, error delimiter, or overload
delimiter.
An interframe space or overload frame starts from here.
8 bits
<3>
(<5>)
Interframe space or overload frame
Overload delimiter
Overload flag (node n)
Overload flag (node m)
Frame
Note
CHAPTER 20 CAN CONTROLLER
Definition
Page 905 of 1509
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