UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1310

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) Oscillation stabilization time select register (OSTS)
The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash
memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
This register can be read or written in 8-bit units.
Reset sets this register to 06H.
Note The oscillation stabilization time and setup time are required when the STOP mode and
Cautions 1. The wait time following release of the STOP mode does not include the time
Remark
OSTS
After reset: 06H
IDLE2 mode are released, respectively.
OSTS2
2. Be sure to set bits 3 to 7 to “0”.
3. The oscillation stabilization time following reset release is 2
f
X
0
0
0
0
1
1
1
1
0
= Main clock oscillation frequency
until the clock oscillation starts ("a" in the figure below) following release of
the STOP mode, regardless of whether the STOP mode is released by reset or
the occurrence of an interrupt request signal.
initial value of the OSTS register = 06H).
Voltage waveform of X1 pin
R/W
OSTS1
0
0
0
1
1
0
0
1
1
Address: FFFFF6C0H
OSTS0
0
0
1
0
1
0
1
0
1
V
SS
Selection of oscillation stabilization time/setup time
2
2
2
2
2
2
2
Setting prohibited
STOP mode release
10
11
12
13
14
15
16
/f
/f
/f
/f
/f
/f
/f
0
X
X
X
X
X
X
X
a
0
OSTS2
10.923 ms
0.341 ms
0.683 ms
1.365 ms
2.730 ms
5.461 ms
21.85 ms
CHAPTER 25 STANDBY FUNCTION
3 MHz
OSTS1
f
X
0.171 ms
0.341 ms
0.683 ms
1.365 ms
2.731 ms
5.461 ms
10.92 ms
6 MHz
OSTS0
16
/f
Note
X
(because the
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