UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 451

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(9) TMT0 option register 1 (TT0OPT1)
The TT0OPT1 register is an 8-bit register that detects overflows, underflows, and count-up/down operations of the
encoder count function.
The TT0OPT1 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
This register can be rewritten even when the TT0CTL0.TT0CE bit = 1.
TT0OPT1
After reset: 00H
Reset (0)
• The TT0EUF bit is set to 1 when the 16-bit counter underflows from 0000H to
• When the TT0CTL2.TT0LDE bit = 1, the TT0EUF bit is set to 1 when the value of
• An overflow interrupt request signal (INTTTOV0) is generated as soon as the
• The TT0EUF bit is not cleared to 0 even if the TT0EUF bit or TT0OPT1 register
• The status of the TT0EUF bit is retained even if the TT0CTL0.TT0CE bit is cleared
• Before clearing the TT0EUF bit to 0 after the INTTTOV0 signal is generated, be
• The TT0EUF bit can be read or written, but it cannot be set to 1 by software.
TT0EUF
Set (1)
FFFFH in the encoder compare mode.
the 16-bit counter is changed from 0000H to the set value of the TT0CCR0 register.
TT0EUF bit is set to 1.
is read when the TT0EUF bit = 1.
to 0 when the TT0CTL2.TT0ECC bit = 1.
sure to confirm (read) that the TT0EUF bit is set to 1.
Setting this bit to 1 does not affect the operation of TMT0.
7
0
R/W
Underflow occurs.
Cleared by writing to TT0EUF bit or when TT0CTL0.TT0CE bit = 0
6
0
Address: FFFFF608H
0
5
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TMT0 underflow detection flag
4
0
3
0
TT0EUF TT0EOF
<2>
<1>
TT0ESF
<0>
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