UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 15

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) ................................................................. 1232
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................. 1256
21.6 Register Configuration ........................................................................................................ 1058
21.7 STALL Handshake or No Handshake................................................................................. 1181
21.8 Register Values in Specific Status ..................................................................................... 1182
21.9 FW Processing ..................................................................................................................... 1184
22.1 Features ................................................................................................................................ 1232
22.2 Configuration........................................................................................................................ 1233
22.3 Registers ............................................................................................................................... 1234
22.4 Transfer Targets................................................................................................................... 1243
22.5 Transfer Modes .................................................................................................................... 1243
22.6 Transfer Types ..................................................................................................................... 1244
22.7 DMA Channel Priorities ....................................................................................................... 1245
22.8 Time Related to DMA Transfer............................................................................................ 1245
22.9 DMA Transfer Start Factors ................................................................................................ 1246
22.10 DMA Abort Factors .............................................................................................................. 1247
22.11 End of DMA Transfer ........................................................................................................... 1247
22.12 Operation Timing.................................................................................................................. 1247
22.13 Cautions ................................................................................................................................ 1251
23.1 Features ................................................................................................................................ 1256
23.2 Non-Maskable Interrupts ..................................................................................................... 1267
23.3 Maskable Interrupts ............................................................................................................. 1272
23.4 Software Exception.............................................................................................................. 1287
23.5 Exception Trap ..................................................................................................................... 1290
21.6.1 USB control registers ..................................................................................................................1058
21.6.2 USB function controller register list .............................................................................................1060
21.6.3 EPC control registers ..................................................................................................................1076
21.6.4 Data hold registers......................................................................................................................1128
21.6.5 EPC request data registers .........................................................................................................1151
21.6.6 Bridge register.............................................................................................................................1166
21.6.7 DMA register ...............................................................................................................................1170
21.6.8 Bulk-in register ............................................................................................................................1174
21.6.9 Bulk-out register..........................................................................................................................1175
21.6.10
21.9.1 Initialization processing ...............................................................................................................1186
21.9.2 Interrupt servicing .......................................................................................................................1189
21.9.3 USB main processing .................................................................................................................1190
21.9.4 Suspend/Resume processing .....................................................................................................1216
21.9.5 Processing after power application .............................................................................................1219
21.9.6 Receiving data for bulk transfer (OUT) in DMA mode .................................................................1222
21.9.7 Transmitting data for bulk transfer (IN) in DMA mode.................................................................1227
23.2.1 Operation ....................................................................................................................................1269
23.2.2 Restore .......................................................................................................................................1270
23.2.3 NP flag ........................................................................................................................................1271
23.3.1 Operation ....................................................................................................................................1272
23.3.2 Restore .......................................................................................................................................1274
23.3.3 Priorities of maskable interrupts..................................................................................................1275
23.3.4 Interrupt control register (xxICn) .................................................................................................1279
23.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5) ...........................................................................1283
23.3.6 In-service priority register (ISPR) ................................................................................................1285
23.3.7 ID flag .........................................................................................................................................1286
23.3.8 Watchdog timer mode register 2 (WDTM2).................................................................................1286
23.4.1 Operation ....................................................................................................................................1287
23.4.2 Restore .......................................................................................................................................1288
23.4.3 EP flag ........................................................................................................................................1289
23.5.1 Illegal opcode..............................................................................................................................1290
23.5.2 Debug trap ..................................................................................................................................1292
Peripheral control registers ....................................................................................................1177