UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 180

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
5.3
memory space. The programmable wait function and bus cycle operation mode for each of these blocks can be
independently controlled in one-block units.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the
Notes 1. CS1 is not provided as an external signal of the V850ES/Jx3-H; it is used internally as a chip select
Memory Block Function
2. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
3. Only the programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB address
4. In the CAN controller version, addresses 03FEC000H to 03FEEFFFH are assigned as a
5. This area is an external memory area in the case of a data write access.
0 3 F F F F F F H
0 3 F E C 0 0 0 H
0 3 F E B F F F H
0 1 0 0 0 0 0 0 H
0 0 F F F F F F H
0 0 8 0 0 0 0 0 H
0 0 7 F F F F F H
0 0 4 0 0 0 0 0 H
0 0 3 F F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 0 0 0 0 0 0 H
signal for the USB.
same area as the on-chip peripheral I/O area.
space.
programmable peripheral I/O area in addresses 03FEC000H to 03FECBFFH.
addresses in a version without a CAN controller is prohibited.
External memory area
External memory area
External memory area
Use prohibited
Figure 5-1. Data Memory Map: Physical Address
(80 KB)
(8 MB)
(4 MB)
(2 MB)
(2 MB)
CS3
CS2
CS0
(CS1
Note 1
)
Programmable peripheral
CHAPTER 5 BUS CONTROL FUNCTION
Internal ROM area
or use prohibited
External memory area
Data-only RAM area
Use prohibited
USB function area
On-chip peripheral
Internal RAM area
Use prohibited
Use prohibited
I/O area (4 KB)
I/O area
(60 KB)
(1 MB)
(1 MB)
Note 3
Note 2
Note 4
Note 5
0 3 F F F F F F H
0 3 F F F 0 0 0 H
0 3 F F E F F F H
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
0 3 F E F 0 0 0 H
0 3 F E E F F F H
0 3 F E C 0 0 0 H
0 0 3 F F F F F H
0 0 3 0 0 0 0 0 H
0 0 2 F F F F F H
0 0 2 8 0 0 0 0 H
0 0 2 7 F F F F H
0 0 2 5 0 0 0 0 H
0 0 2 4 F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 0 0 0 0 0 0 H
Use of these
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