UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 776

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
18.5 Interrupt Request Signals
default, and the priority of the transmission enable interrupt request signal is lower.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
CSIFn can generate the following two types of interrupt request signals.
• Reception completion interrupt request signal (INTCFnR)
• Transmission enable interrupt request signal (INTCFnT)
Of these two interrupt request signals, the reception completion interrupt request signal has the higher priority by
(1) Reception completion interrupt request signal (INTCFnR)
(2) Transmission enable interrupt request signal (INTCFnT)
When receive data is transferred to the CFnRX register while reception is enabled, the reception completion
interrupt request signal is generated.
This interrupt request signal can also be generated if an overrun error occurs.
When the reception completion interrupt request signal is acknowledged and the data is read, read the CFnSTR
register to check that the result of reception is not an error.
In the single transfer mode, the INTCFnR interrupt request signal is generated upon completion of transmission,
even when only transmission is executed.
In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from the
CFnTX register and, as soon as writing to CFnTX has been enabled, the transmission enable interrupt request
signal is generated.
In the single transmission and single transmission/reception modes, the INTCFnT interrupt is not generated.
Table 18-2. Interrupts and Their Default Priority
Reception complete
Transmission enable
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Interrupt
Priority
High
Low
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