UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1084

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) UF0 SNDSIE register (UF0SDS)
UF0SDS
This register performs manipulation such as no handshake. It can directly manipulate the pins of SIE.
This register can be read or written in 8-bit units.
Be sure to clear bit 2 to “0”. If it is set to 1, the operation is not guaranteed.
Bit position
3
0
7
0
SNDSTL
RSUMIN
Bit name
6
0
This bit makes Endpoint0 issue a STALL handshake. Setting this bit to 1 if a request for
CPUDEC processing is not supported by the system results in a STALL handshake
response. If an unsupported wValue is sent by the SET_CONFIGURATION or
SET_INTERFACE request, the hardware sets this bit to 1. If a problem occurs in
Endpoint0 due to overrun of an automatically executed request, this bit is also set to 1.
However, the E0HALT bit of the UF0E0SL register is not set to 1.
This bit is cleared to 0 and the handshake response to the bus is other than STALL when
the next SETUP token is received. To set the SNDSTL bit to 1 by FW, do not write data to
the UF0E0W register. Depending on the timing of setting this bit, the STALL response is
not made in time, and it may be made to the next transfer after a NAK response has been
made.
Setting this bit is valid only while an FW-executed request is under execution when this bit
is set to 1. It is automatically cleared to 0 when the next SETUP token is received.
Remark The SNDSTL bit is valid only for an FW-executed request.
This bit outputs the Resume signal onto the USB bus. Writing this bit is invalid unless the
RMWK bit of the UF0DSTL register is set to 1.
While this bit is set to 1, the Resume signal continues to be generated. Clear this bit to 0
by FW after a specific time has elapsed. Because the signal is internally sampled at the
clock, the operation is guaranteed only while CLK is supplied. Care must be exercised
when CLK of the system is stopped.
5
0
1: Respond with STALL handshake.
0: Do not respond with STALL handshake (default value).
1: Generate the Resume signal.
0: Do not generate the Resume signal (default value).
4
0
SNDSTL
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
2
0
Function
1
0
RSUMIN
0
00200008H
Address
Page 1084 of 1509
After reset
00H