UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 687

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
Remark
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Other than above
ADA0FR3 to
ADA0FR0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits
Stabilization time:
Conversion time:
f
In the high-speed conversion mode, the conversion is started after the stabilization time elapses after the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75
μ
ends.
In continuous conversion mode, the stabilization time is inserted only before the first conversion, and not
inserted after the second conversion (the A/D converter remains running).
Cautions 1. Set as 2.17
XX
s). The A/D conversion end interrupt request signal (INTAD) is generated immediately after the conversion
Table 15-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)
:
2. In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM,
52/f
104/f
156/f
208/f
260/f
312/f
364/f
416/f
468/f
520/f
572/f
624/f
676/f
728/f
780/f
832/f
(+ Stabilization Time)
XX
and ADA0PFT registers and trigger input are prohibited during the stabilization time.
Conversion Time
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
(+26/f
(+52/f
(+78/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
(+100/f
XX
XX
XX
)
A/D converter setup time (1
Actual A/D conversion time (2.17 to 9.75
Main clock frequency
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
μ
s ≤ conversion time ≤ 9.75
Setting prohibited
2.17
3.25
4.33
5.42
6.50
7.58
8.67
9.75
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
μ
μ
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
s
48 MHz
A/D Conversion Time
μ
Setting prohibited
s or longer)
μ
s.
Setting prohibited
3.25
4.88
6.50
8.13
9.75
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
μ
μ
μ
μ
μ
μ
s)
s
s
s
s
s
32 MHz
CHAPTER 15 A/D CONVERTER
2.17
4.33
6.50
8.67
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
μ
μ
μ
μ
s
s
s
s
24 MHz
Page 687 of 1509