UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 242

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TAAmIOC0
(c) TAAm I/O control register 0 (TAAmIOC0)
(d) TAAn counter read buffer register (TAAnCNT)
(e) TAAn capture/compare register 0 (TAAnCCR0)
(f) TAAn capture/compare register 1 (TAAnCCR1)
By reading the TAAnCNT register, the count value of the 16-bit counter can be read.
If the TAAnCCR0 register is set to D
Interval = (D
Usually, the TAAnCCR1 register is not used in the interval timer mode. However, the set value of
the TAAnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt
request signal (INTTAAnCC1) is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt mask flag
(TAAnCCMK1).
Remarks 1.
0
2.
Figure 7-9. Register Settings for Interval Timer Mode Operation (2/2)
0
TAAm I/O control register 1 (TAAmIOC1), TAAm I/O control register 2 (TAAmIOC2),
and TAAm option register 0 (TAAmOPT0) are not used in the interval timer mode.
m = 0 to 3, 5
n = 0 to 5
0
+ 1) × Count clock cycle
0
0
0
TAAmOL1
, the interval is as follows.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0/1
TAAmOE1TAAmOL0 TAAmOE0
0/1
0/1
0/1
0: Disables TOAAm0 pin output
1: Enables TOAAm0 pin output
Setting of output level with
operation of TOAAm0 pin disabled
0: Low level
1: High level
0: Disables TOAAm1 pin output
1: Enables TOAAm1 pin output
Setting of output level with
operation of TOAAm1 pin disabled
0: Low level
1: High level
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