UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1219
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
21.9.5 Processing after power application
example is given below.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The processing to be performed after power application differs depending on the configuration of the system. One
Notes 1. Use one general-purpose port pin for the signal that controls switching of the pull-up resistor of the
Remark
BUSRST = 1 (UF0IS0)
Initialization of request
DFLT = 1 (UF0MODS)
Pull-up processing of
Controlling port
Resume
2. The input mode or control mode of the general-purpose port pin allocated in Note 1 may be selected
Pull-up processing
of D+ active
D+ inactive
data register
Connection
USB bus.
as the default value. Note the active level of pull-up processing of D+ on power application.
♦: Processing by hardware
START
(a)
detected?
Figure 21-31. Example of Processing After Power Application/Power Failure (1/3)
Yes
Note 1
Note 1
Note 2
:
See Figure 21-15 Initialization
Settings of Request Data Register.
No
(a) Processing after power application (1/2)
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
Initialization of request data
Controlling port
START
register
Note 2
:
See Figure 21-15 Initialization
Settings of Request Data Register.
Page 1219 of 1509
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