UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 327

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the valid edge input to the TIAA10 pin is detected, the count value is stored in the capture register 0
(TAA1CCR0 and TAA0CCR0), and capture interrupt 0 signal (INTTAA1CC0) is issued.
up to FFFFFFFFH, the overflow interrupt (INTTAA0OV) is generated at the next clock and the overflow flag
(TAA0OVF) is set to 1. The timer counter is cleared to 00000000H and continues counting up.
edge input to the TIAA10 pin.
recommended to mask this interrupt because it cannot be used as an overflow interrupt of the 32-bit counter.
The counting operation is started when the TAA1CTL.TAA1CE bit is set to 1 and the count clock is supplied.
The timer counter continues the counting operation in synchronization with the count clock. When it counts
The overflow flag (TAA0OVF) is cleared by an instruction issued from the CPU that writes “0” to it.
Because the free-running timer mode is set, the timer counter cannot be cleared by detection of the valid
Using TOAA10 output is prohibited because it alternately functions as the TIAA10 input.
Capture register 1 (TAA1CCR1 and TAA0CCR1) also operates in the same manner.
If the lower timer counter (TAA1) overflows, an overflow interrupt (TAA1OVF) is generated. However, it is
Lower capture interrupt 0
Higher capture register 0
Higher capture register 1
Lower capture register 0
Lower capture register 1
Figure 7-52. Example of Basic Timing When TAA1 and TAA0 Are Connected in Cascade
Operation enable bit
Capture interrupt 1
Overflow interrupt
(INTTAA1CC0)
(INTTAA1CC1)
(INTTAA0OV)
32-bit counter
TIAA10 input
(TAA1CCR0)
(TAA0CCR0)
TIAA11 input
(TAA1CCR1)
(TAA0CCR1)
FFFFFFFFH
Overflow flag
00000000H
(TAA0OVF)
(
TAA1CE)
0000
0000
0000
0000
D
0a0b
D
D
Pulse interval
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
1a1b
0c0d
Cleared to 0 by
CLR instruction
D
D
−
Pulse interval
0b
0a
D
D
1c1d
0a0b
D
0c0d
D
D
−
D
Pulse interval
1b
1a
0e0f
D
D
1a1b
1c1d
D
D
−
D
0d
0c
D
0e0f
0c0d
Pulse interval
D
1e1f
Pulse interval
CLR instruction
Cleared to 0 by
D
D
D
0g0h
−
1d
1c
D
D
D
D
1c1d
−
1e1f
0f
0e
D
D
0c0d
0g0h
Pulse interval
D
1g1h
Pulse interval
D
D
D
−
0i0j
1f
1e
D
CLR instruction
Cleared to 0 by
−
D
D
1c1d
0h
0g
D
D
0g0h
1g1h
D
0i0j
D
D
1h
1g
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D
D
0j
0i