UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 189

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
5.5
5.5.1
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Data wait control register 0 (DWC0)
Wait Function
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle
that is executed for each CS space.
The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data
wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
Programmable wait function
Note The DW12 to DW10 bits set wait of access to the USB function area.
Caution Be sure to clear bits 15, 11, 7, and 3 to “0”.
It is recommended to set the DW12 to DW10 bits to 001B (1 wait).
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not
DWC0
After reset:
always accessed without a wait state. The on-chip peripheral I/O area is also not subject to
programmable wait, and only wait control from each peripheral function is performed.
access an external memory area until the initial settings of the DWC0 register are complete.
DWn2
15
7777H
0
7
0
0
0
0
0
1
1
1
1
DW12
DW32
DWn1
14
0
0
1
1
0
0
1
1
6
R/W
Note
DW11
DW31
DWn0
CS3
Address:
13
5
0
1
0
1
0
1
0
1
Note
DW10
None
1
2
3
4
5
6
7
DW30
FFFFF484H
12
4
Note
Number of wait states inserted in
11
0
0
3
CSn space (n = 0 to 3)
CHAPTER 5 BUS CONTROL FUNCTION
DW22
DW02
10
2
DW21
DW01
CS0
CS2
1
9
DW20
DW00
0
8
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