UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1252

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
22.13 Cautions
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Caution for VSWC register
(3) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1)
(2) Caution for reading DCHCn.TCn bit (n = 0 to 3)
When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the
VSWC register.
When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register,
the operation is not correctly performed (for details of the VSWC register, see 3.4.9 (1) (a) System wait control
register (VSWC)).
The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific timing.
To accurately clear the TCn bit, add the following processing.
(a) When waiting for completion of DMA transfer by polling TCn bit
(b) When reading TCn bit in interrupt servicing routine
Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not
be initialized. To accurately initialize the channel, execute either of the following two procedures.
(a) Temporarily stop transfer of all DMA channels
<4> Set the INITn bit of the channel to be forcibly terminated to 1.
<5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit read in
<6> After the operation in <5>, write the Enn bit value to the DCHCn register.
<7> Enable interrupts (EI).
Caution Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels
Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more
times.
Execute reading the TCn bit three times.
Initialize the channel executing DMA transfer using the procedure in <1> to <7> below.
Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other processing
programs do not expect that the TCn bit is 1.
<1> Disable interrupts (DI).
<2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer the
<3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To
value to a general-purpose register.
clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA transfer
(transfer source/destination) is the internal RAM, execute the instruction three times.
<2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0.
Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of
whose DMA transfer has been normally completed between <2> and <3>.
transfer is not the internal RAM).
• Clear DCHC0.E00 bit to 0.
• Clear DCHC1.E11 bit to 0.
• Clear DCHC2.E22 bit to 0.
• Clear DCHC2.E22 bit to 0 again.
CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
Page 1252 of 1509