UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 390
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (9Mb)
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
(TIAB00 pin input)
External trigger input
INTTABnCC0 signal
INTTABnCCk signal
(only when software
TABnCCR0 register
TABnCCRk register
TOABn0 pin output
(a) Notes on rewriting TABnCCRm register
TOABnk pin output
trigger is used)
To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
When the TABnCCR0 register is rewritten from D
D
greater than D
than D
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
pin. When the count value matches D
TOABnk pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark
16-bit counter
Note TAB1: TRGAB1 pin
00
TABnCE bit
> D
FFFFH
0000H
01
01
Note
and less than D
and D
k = 1 to 3,
n = 0, 1
k1
k0
and less than D
> D
k1
Delay
(D
, if the TABnCCRk register is rewritten when the count value of the 16-bit counter is
k0
00
)
Active level width
D
, each set value is reflected as soon as the register has been rewritten and
(D
k0
00
k0
− D
D
k1
k0
and if the TABnCCR0 register is rewritten when the count value is greater
, the counter generates the INTTABnCCk signal and asserts the TOABnk
D
k0
D
00
+ 1)
00
01
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
, the counter generates the INTTABnCC0 signal, deasserts the
(10000H + D
00
D
k0
to D
Delay
01
and the TABnCCRk register from D
D
k1
00
)
Active level width
D
(D
k1
01
− D
D
k1
k1
D
+ 1)
01
D
01
Delay
(D
k1
Active level width
D
)
(D
k1
01
Page 390 of 1509
− D
k0
k1
to D
D
+ 1)
01
k1
where
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