UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 222

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(4) TAAn I/O control register 1 (TAAnIOC1)
The TAAnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIAAn0,
TIAAn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 3, 5)
TAAnIOC1
After reset: 00H
Cautions 1.
TAAnIS3
TAAnIS1
0
0
1
1
0
0
1
1
7
0
2.
TAAnIS2
TAAnIS0
R/W
Rewrite
TAAnCTL0.TAAnCE bit = 0.
written when the TAAnCE bit = 1.)
mistakenly performed, clear the TAAnCE bit to 0 and then
set the bits again.
The TAAnIS3 to TAAnIS0 bits are valid only in the free-
running timer mode and the pulse width measurement
mode.
performed.
6
0
0
1
0
1
0
1
0
1
Address:
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TIAAn1 pin) valid edge setting
Capture trigger input signal (TIAAn0 pin) valid edge setting
In all other modes, a capture operation is not
the
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
5
0
TAAnIS3
TAA0IOC1 FFFFF633H, TAA1IOC1 FFFFF643H,
TAA2IOC1 FFFFF653H, TAA3IOC1 FFFFF663H,
TAA5IOC1 FFFFF683H
4
0
TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0
to
3
TAAnIS0
(The same value can be
2
bits
If rewriting was
1
when
0
the
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