UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1222

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
21.9.6 Receiving data for bulk transfer (OUT) in DMA mode
controlled when DMA is used. Endpoint4 can also be controlled in the same sequence. To use this flowchart as the
control flow of Endpoint4, therefore, read the bit names of Endpoint2 in the flowchart as those of Endpoint4. The control
flowchart shown below illustrates how remaining data is read by the CPU.
DMA request signal for Endpoint2, instead of an interrupt request (INTUSBF0), becomes active. This DMA request signal
for Endpoint2 operates according to the setting of the MODEn bit of the UF0IDR register (n = 0, 1). If all the data stored in
the UF0BO1 register has been read by DMA, the DMA request signal for Endpoint2 becomes inactive. In this status, if
data for the next bulk transfer (OUT) has been correctly received, the DMA request signal for Endpoint2 becomes active
again. If the data for bulk transfer (OUT) that has been received is equal to or less than the FIFO size, a Short interrupt
request is issued and the INTUSBF0 (EP2_ENDINT) signal becomes active, as soon as reading the data by DMA is
completed. To read data by DMA again, set the DQBO1MS bit to 1 again. If DMA is completed by the DMA end signal for
Endpoint2, the DQBO1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint2 becomes
inactive. At the same time, the DMA_END interrupt request is issued. If data remains in the UF0BO1 register at this time,
DMA can be started again by setting the DQBO1MS bit of the UF0IDR register again. However, the data for bulk transfer
(OUT) is always equal to or less than the FIFO size. Consequently, a Short interrupt request is issued, the INTUSBF0
(EP2_ENDINT) signal becomes active, the DQBO1MS bit is cleared, and the DMA request signal for Endpoint2 becomes
inactive, as soon as the data is read by DMA.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Bulk transfer (OUT) is allocated to Endpoint2 and Endpoint4. The flowchart shown below illustrates how Endpoint2 is
If data for bulk transfer (OUT) has been correctly received by setting the DQBO1MS bit of the UF0IDR register to 1, the
Cautions 1. The DMA request signal for Endpoint n (n = 2, 4) becomes active in the demand mode (MODE1
2. For a DMA transfer for which the data for a bulk transfer (OUT) is a Short packet (63 bytes or less),
and MODE0 bits of the UF0IDR register = 10), as long as there is data to be transferred.
after the transfer finishes, clear the UF0IC0.SHORTC and UF0IS0.SHORT bits.
If the SHORT bits are not cleared, the DMASTOP_EPnB signal is asserted and the next DMA
transfer operation is not performed.
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
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