UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1266
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (9Mb)
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time.
2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by
Restored PC:
nextPC:
(Restored PC − 4).
The highest priority is 0.
The priority order of non-maskable interrupt is INTWDT2 > NMI.
The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt
servicing is started. Note, however, that the restored PC when a non-maskable or
maskable interrupt is acknowledged while one of the following instructions is being
executed does not become the nextPC (if an interrupt is acknowledged during interrupt
execution, execution stops, and then resumes after the interrupt servicing has finished).
• Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
• Division instructions (DIV, DIVH, DIVU, DIVHU)
• PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack
The PC value that starts the processing following interrupt/exception processing.
pointer is updated)
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Page 1266 of 1509
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