UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 175

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
4.5.2
the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
P91 to P97
Port 9L latch
Cautions on bit manipulation instruction for port n register (Pn)
0
P90
0
When the P90 pin is an output port, the P91 to P97 pins are input ports (all pin statuses are high level),
and the value of the port latch is 00H, if the output of the P90 pin is changed from low level to high level
via a bit manipulation instruction, the value of the port latch is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are
the output latch and pin status, respectively.
A bit manipulation instruction is executed in the following order in the V850ES/JG3-H and V850ES/JH3-
H.
<1> The Pn register is read in 8-bit units.
<2> The targeted bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the value of the output latch (0) of the P90 pin, which is an output port, is read, while the pin
statuses of the P91 to P97 pins, which are input ports, are read. If the pin statuses of the P91 to P97
pins are high level at this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
0
Bit manipulation instruction for P90 bit
<1> P9L register is read in 8-bit units.
<2> Set (1) P90 bit.
<3> Write the results of <2> to the output latch of P9L register in 8-bit units.
0
• In the case of P90, an output port, the value of the port latch (0) is read.
• In the case of P91 to P97, input ports, the pin status (1) is read.
0
Pin status: High level
Low-level output
Figure 4-6. Bit Manipulation Instruction (P90 Pin)
0
0
0
Bit manipulation
instruction
(set1 0, P9L[r0])
is executed for
P90 bit.
P91 to P97
Port 9L latch
1
P90
1
CHAPTER 4 PORT FUNCTIONS
1
1
1
Pin status: High level
High-level output
1
Page 175 of 1509
1
1