UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1111

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(27) UF0 DMA status 0 register (UF0DMS0)
UF0DMS0
Bit position
This register indicates the DMA status of Endpoint1 to Endpoint4.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4)
and the current setting of the interface.
5
4
3
2
7
0
DQE4
DQE3
DQE2
DQE1
Bit name
6
0
DQE4
This bit indicates that a DMA read request is being issued from Endpoint4 to memory.
This bit indicates that a DMA write request is being issued from memory to Endpoint3.
Note that, even if data is in Endpoint3 (when the FIFO is not full and after the BKI2DED
bit has been set to 1), the DMA request signal becomes active immediately and DMA
transfer is started when the DQBI2MS bit of the UF0IDR register is set to 1.
This bit indicates that a DMA read request is being issued from Endpoint2 to memory.
This bit indicates that a DMA write request is being issued from memory to Endpoint1.
Note that, even if data is in Endpoint1 (when the FIFO is not full and after the BKI1DED
bit has been set to 1), the DMA request signal becomes active immediately and DMA
transfer is started when the DQBI1MS bit of the UF0IDR register is set to 1.
5
1: DMA read request from Endpoint4 is being issued.
0: DMA read request from Endpoint4 is not being issued (default value).
1: DMA write request for Endpoint3 is being issued.
0: DMA write request for Endpoint3 is not being issued (default value).
1: DMA read request from Endpoint2 is being issued.
0: DMA read request from Endpoint2 is not being issued (default value).
1: DMA write request for Endpoint1 is being issued.
0: DMA write request for Endpoint1 is not being issued (default value).
DQE3
4
DQE2
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
DQE1
2
Function
1
0
0
0
0020004EH
Address
Page 1111 of 1509
After reset
00H