UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 833

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) IIC function expansion registers 0 to 2 (IICX0 to IICX2)
(6) I
The IICXn registers set I
These registers can be read or written in 8-bit or 1-bit units.
Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and
the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 19.4 (6) I
method) (m = 0, 1).
Set the IICXn registers when the IICCn.IICEn bit = 0.
Reset sets these registers to 00H.
The I
For example, the I
calculated using following expression.
The clock to be selected can be set by combining of the SMCn, CLn1, and CLn0 bits of the IICCLn register, the
CLXn bit of the IICXn register, and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (n = 0 to 2,
m = 0, 1).
2
C0n transfer clock setting method
f
2
SCL
C0n transfer clock frequency (f
m = 24, 48, 72, 96, 108, 120, 144, 172, 192, 240, 264, 344, 352, 396, 440, 516, 688, 860 (see Table 19-2
T:
t
t
f
R
F
SCL
= 1/(m × T + t
:
IICXn
(n = 0 to 2)
:
After reset: 00H
= 1/(198 × 52 ns + 200 ns + 50 ns) ≅ 94.7 kHz
Clock Settings).
1/f
SCL0n pin rise time
SCL0n pin fall time
XX
SCL0n
2
C0n transfer clock frequency (f
SCL0n inversion
0
R
2
+ t
t
C0n function expansion (valid only in the high-speed mode).
R
F
)
R/W
0
m/2 × T
SCL
Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H, IICX2 FFFFFDA5H
) is calculated using the following expression (n = 0 to 2).
0
m × T + t
SCL0n inversion
SCL
0
R
+ t
) when f
F
t
F
0
XX
m/2 × T
= 19.2 MHz, m = 198, t
0
SCL0n inversion
0
2
C0n transfer clock setting
R
CLXn
CHAPTER 19 I
< >
= 200 ns, and t
Page 833 of 1509
F
= 50 ns is
2
C BUS