UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 196
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 196 of 1512
- Download datasheet (9Mb)
V850ES/JG3-H, V850ES/JH3-H
5.8
executed in the external bus cycle.
instruction fetch (successive).
accesses due to bus size limitations.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are
Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and
An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between
Bus Priority
Priority
High
Low
Bus hold
DMA transfer
Operand data access
Instruction fetch (branch)
Instruction fetch (successive)
Table 5-5. Bus Priority
External Bus Cycle
CHAPTER 5 BUS CONTROL FUNCTION
External device
DMAC
CPU
CPU
CPU
Bus Master
Page 196 of 1509
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