UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 73
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 73 of 1512
- Download datasheet (9Mb)
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) On-chip peripheral I/O area
(4) External memory area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-chip
peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword units in
13 MB (00100000H to 001FFFFFH, 00400000H to 00FFFFFFH) are allocated as the external memory area. For
details, see CHAPTER 5 BUS CONTROL FUNCTION.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits
3. Addresses not defined as registers are reserved for future expansion. The operation is
4. The internal ROM/RAM area and on-chip peripheral I/O area are assigned to successive
the order of lower area and higher area, with the lower 2 bits of the address ignored.
are undefined when the register is read, and data is written to the lower 8 bits.
undefined and not guaranteed when these addresses are accessed.
addresses.
When accessing the internal ROM/RAM area by incrementing or decrementing addresses
using a pointer operation or such, be careful not to access the on-chip peripheral I/O area by
mistakenly extending over the internal ROM/RAM area boundary.
Physical address space
0 3 F F F F F F H
0 3 F F F 0 0 0 H
Figure 3-11. On-Chip Peripheral I/O Area
On-chip peripheral I/O area
(4 KB)
Logical address space
F F F F F F F F H
F F F F F 0 0 0 H
CHAPTER 3 CPU FUNCTION
Page 73 of 1509
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