UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1116

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Remark
Bit position
2, 1
0
n = 1, 2
BKInDED
E0DED
Bit name
Set these bits to 1 when writing transmit data to the UF0BIn register has been completed.
When these bits are set to 1, the FIFO is toggled as soon as possible, the BKInNK bit is
set to 1, and data is transferred.
These bits control the FIFO on the CPU side.
If the BKInCC bit of the UF0FIC0 register is set to 1 and then these bits are set to 1
(counter of UF0BIn register = 0), a Null packet (with a data length of 0) is transmitted.
If data exists in the UF0BIn register and if these bits are set to 1 (counter of UF0BIn
register ≠ 0), and if the FIFO is not full, a short packet is transmitted.
If the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA, with
the PIO or BKInT bit set to 1, the hardware starts data transmission even if these bits are
not set to 1.
If the FIFO on the CPU side of the UF0BIn register becomes full as a result of DMA, with
the BKInT bit cleared to 0, be sure to set these bits to 1 (see 21.6.3 (3) UF0 EPNAK
register (UF0EN)).
Set this bit to 1 to transmit data of the UF0E0W register. When this bit is set to 1, the
EP0NKW bit is set to 1 and data is transferred.
If the EP0WC bit of the UF0FIC0 register is set to 1 and if this bit is set to 1 (counter of
UF0E0W register = 0 and bit 1 of UF0EPS0 register = 1), a Null packet (with a data length
of 0) is transmitted.
If data exists in the UF0E0W register and if this bit is set to 1 (counter of UF0E0W register
≠ 0 and bit 1 of the UF0EPS0 register = 1), and if the FIFO is not full, a short packet is
transmitted.
1: Transmit a short packet.
0: Do not transmit a short packet (default value).
1: Transmit a short packet.
0: Do not transmit a short packet (default value).
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
Function
Page 1116 of 1509
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