UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 983
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
20.9.2 Reading reception data
procedures shown in Figures 20-49 and 20-50.
to store data in the message buffer and at the end of this storing processing. During this storing processing, the
C0MCTRLm.MUC bit of the message buffer is set (1) (refer to Figure 20-29).
CPU is prohibited from rewriting the C0MCTRLm.RDY bit of the message buffer in which the data is to be stored.
Completion of this data storing processing may be delayed by a CPU’s access to any message buffer.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
CAN standard
ID format
If it is necessary to consistently read data from the CAN message buffer by software, follow the recommended
While receiving a message, the CAN module sets the C0MCTRLm.DN bit two times, at the beginning of the processing
Before the data is completely stored, the receive history list is written. During this data storing period (MUC bit = 1), the
Remark
C0INTS.CINTS1
bit
INTC0REC
signal
Operation of CAN controller
MUC bit
DN bit
m = 0 to 31
(1)
(11)
ID
Figure 20-29. DN and MUC Bit Setting Period (in Standard ID Format)
(1)
(1)
(1)
DLC
(4)
DATA0-DATA7
(0-64)
CRC
(16)
ACK EOF
(2)
(7)
DATA, DLC, ID → Message buffer
The DN and MUC bits are
set (1) at the same time.
Message stored
CHAPTER 20 CAN CONTROLLER
IFS
The DN bit is set (1) and the
MUC bit is cleared (0) at the
same time.
Recessive
Dominant
Page 983 of 1509
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