UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1376
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UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1376 of 1512
- Download datasheet (9Mb)
V850ES/JG3-H, V850ES/JH3-H
31.4.4 Selection of communication mode
the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated
flash programmer.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
In the V850ES/JG3-H and V850ES/JH3-H, the communication mode is selected by inputting pulses (12 pulses max.) to
The following shows the relationship between the number of pulses and the communication mode.
Note The number of clocks is as follows depending on the communication mode.
Caution
0
8
9
11
12
Other
TXDC0 (output)
FLMD0 Pulse
RXDC0 (input)
RESET (input)
FLMD1 (input)
FLMD0 (input)
When UARTC0 is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash programmer after receiving the FLMD0 pulse.
V
DD
UARTC0
CSIF0
CSIF3
CSIF0 + HS
CSIF3 + HS
RFU
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
Communication Mode
Power on
Figure 31-9. Selection of Communication Mode
released
Reset
Oscillation
stabilized
Communication rate: 9,600 bps (after reset), LSB first
V850ES/Jx3-H performs slave operation, MSB first
V850ES/Jx3-H performs slave operation, MSB first
V850ES/Jx3-H performs slave operation, MSB first
V850ES/Jx3-H performs slave operation, MSB first
Setting prohibited
Communication
mode selected
(Note)
Flash control command communication
Remarks
CHAPTER 31 FLASH MEMORY
(erasure, write, etc.)
Page 1376 of 1509
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