UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 63
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
3.3
3.3.1
programmer is connected, but it must be input from an external circuit in the self-programming mode.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The V850ES/JG3-H and V850ES/JH3-H have the following operation modes.
(1) Normal operation mode
(2) Flash memory programming mode
(3) On-chip debug mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, make sure that a low level is input to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
Operation Modes
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
In this mode, the internal flash memory can be programmed by using a flash programmer.
The V850ES/JG3-H and V850ES/JH3-H are provided with an on-chip debug function that employs the JTAG (Joint
Test Action Group) communication specifications.
For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.
Specifying operation mode
Remark
Operation When Reset Is Released
FLMD0
H
H
L
L: Low-level input
H: High-level input
×: Don’t care
FLMD1
H
×
L
Normal operation mode
Flash memory programming mode
Setting prohibited
Operation Mode After Reset
CHAPTER 3 CPU FUNCTION
Page 63 of 1509
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