UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 383
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
8.5.4
edge of the external trigger input is detected, TABn starts counting, and outputs a one-shot pulse from the TOABn1 to
TOABn3 pins.
is used, the TOABn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the
counter is stopped (waiting for a trigger).
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
In the one-shot pulse output mode, TABn waits for a trigger when the TABnCTL0.TABnCE bit is set to 1. When the valid
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger
TIAB00 pin
One-shot pulse output mode (TABnMD2 to TABnMD0 bits = 011)
Note TAB1: TRGAB1 pin
Remark
Note
Count clock
selection
Software trigger
generation
n = 0, 1
TABnCE bit
detector
Edge
Figure 8-20. Configuration in One-Shot Pulse Output Mode
Count start
control
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
CCR1 buffer
TABnCCR1
register
register
CCR0 buffer register
TABnCCR0 register
Match signal
16-bit counter
CCR2 buffer
TABnCCR2
register
register
Match signal
CCR3 buffer
TABnCCR3
register
register
Match signal
Match signal
Transfer
Transfer
Transfer
Clear
Transfer
S
R
S
R
S
R
S
R
controller
controller
controller
controller
(RS-FF)
(RS-FF)
(RS-FF)
(RS-FF)
Output
Output
Output
Output
INTTABnCC1 signal
INTTABnCC2 signal
INTTABnCC3 signal
INTTABnCC0 signal
Page 383 of 1509
TOABn1 pin
TOABn2 pin
TOABn3 pin
TOABn0 pin
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