UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 181
UPD70F3771GF-GAT-AX
Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet
1.UPD70F3760GC-UEU-AX.pdf
(1512 pages)
Specifications of UPD70F3771GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-H, V850ES/JH3-H
5.4
5.4.1
5.4.2
size can be set to 8 bits and 16 bits only.
CS3.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
The following table shows the number of basic clocks required for accessing each resource.
Notes 1. V850ES/JH3-H only
Remark
Each external memory area selected by memory block CSn can be set by using the BSC register. However, the bus
The external memory area of the V850ES/JG3-H and V850ES/JH3-H is selected by memory blocks CS0, CS2, and
(1) Bus size configuration register (BSC)
Bus Access
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access
Number of clocks for access
Bus size setting function
Caution Be sure to set bits 14, 12, 10, 8, and 2 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.
2. Increases by 1 if a conflict with a data access occurs.
Unit: Clocks/access
an external memory area until the initial settings of the BSC register are complete.
After reset:
BSC
Area (Bus Width)
BSn0
15
5555H
0
7
0
0
1
8 bits
16 bits
BS30
CS3
Data bus width of
14
1
6
R/W
Internal ROM (32 Bits)
Address:
13
0
0
5
1
3
5
memory block CSn
BS20
FFFFF066H
CS2
12
1
4
11
0
0
Internal RAM (32 Bits)
3
space (n = 0, 2, 3)
CHAPTER 5 BUS CONTROL FUNCTION
1
2
Note 2
Note 1
10
1
1
2
1
9
0
1
0
External Memory (16 Bits)
Multiplexed
BS00
CS0
1
8
0
3 + n
3 + n
3 + n
Page 181 of 1509
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Note 1
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