UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 88

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

86
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR = 1)
(b) Clear condition (PRERR = 0)
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
(i) When data is written to a special register without writing anything to the PRCMD register (when <5> is
(ii) When data is written to a peripheral I/O register other than a special register (including execution of a
Remark
(i) When 0 is written to the PRERR flag of the SYS register
(ii) When the system is reset
executed without executing <4> in 3.4.8 (1) Setting special register)
bit manipulation instruction) after writing data to the PRCMD register (if <5> in 3.4.8 (1) Setting
special register is not the setting of a special register)
After reset:
SYS
2. If data is written to the PRCMD register, which is not a special register, immediately after a
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the
write access takes precedence).
write access to the PRCMD register, the PRERR bit is set to 1.
If a peripheral I/O register is read (excluding the bit manipulation instructions) or the internal
RAM is accessed after the PRCMD register is written and before the special register is written,
the PRERR flag is not set and setting data can be written to the special registers other than the
WDTM register (i.e., the PCC and PSC registers).
PRERR
00H
0
1
0
Protection error did not occur.
Protection error occurred.
R/W
0
Address:
CHAPTER 3 CPU FUNCTION
User’s Manual U15905EJ2V1UD
0
FFFFF802H
Detects protection error
0
0
0
0
PRERR
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