UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 223

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Valid edge select registers 0 and 1 (SES0 and SES1)
These registers specify the valid edge of an external interrupt request (INTP00, INTP01, INTP10, INTP11, TI0,
TI1, TCLR10, and TCLR11) from an external pin.
The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge
independently for each pin.
Each of these registers can be read or written in 8-bit units.
These registers are cleared to 00H after reset.
Caution The various bits of the SESn register must not be changed during timer operation. If they
(n = 0, 1)
are to be changed, they must be changed after setting the TMCEn bit of the TMCn0 register
to 0.
guaranteed.
SESn
After reset:
If the SESn register is overwritten during timer operation, operation cannot be
IESn11
IESn01
TESn1
CESn1
TESn1
00H
7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
R/W
TESn0
IESn10
IESn00
CESn0
TESn0
6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address:
User’s Manual U15905EJ2V1UD
CESn1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
5
SES0 FFFFF609H
CESn0
4
Valid edge of INTPn1 pin
Valid edge of INTPn0 pin
Valid edge of TCLRn pin
Valid edge of TIn pin
IESn11
3
IESn10
SES1 FFFFF619H
2
IESn01
1
IESn00
0
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