UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 320

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

318
(4) Receive operation
The awaiting reception state is set by setting the UARTCAEn bit to 1 in the ASIMn register and then setting the
RXEn bit to 1 in the ASIMn register. To start the receive operation, first perform start bit detection. The start
bit is detected by sampling the RXDn pin.
sequentially in the receive shift register according to the baud rate that was set. A reception completion
interrupt (INTSRn) is generated each time the reception of one frame of data is completed. Normally, the
receive data is transferred from receive buffer register n (RXBn) to memory by this interrupt servicing.
(a) Reception enabled state
(b) Starting a receive operation
(c) Reception completion interrupt
The receive operation is set to the reception enabled state by setting the RXEn bit in the ASIMn register to
1.
• RXEn bit = 1: Reception enabled state
• RXEn bit = 0: Reception disabled state
In reception disabled state, the reception hardware stands by in the initial state. At this time, the contents
of receive buffer register n (RXBn) are retained, and no reception completion interrupt or reception error
interrupt is generated.
A receive operation is started by the detection of a start bit.
The RXDn pin is sampled using the serial clock from baud rate generator n (BRGn).
When RXEn = 1 in the ASIMn register and the reception of one frame of data is completed (the stop bit is
detected), a reception completion interrupt (INTSRn) is generated and the receive data within the receive
shift register is transferred to RXBn at the same time.
Also, if an overrun error (OVEn) occurs, the receive data at that time is not transferred to receive buffer
register n (RXBn), and either a reception completion interrupt (INTSRn) or a reception error interrupt
(INTSREn) is generated (the receive data within the receive shift register is transferred to RXBn)
according to the ISRMn bit setting in the ASIMn register.
Even if a parity error (PEn) or framing error (FEn) occurs during a reception operation, the receive
operation continues until stop bit is received, and after reception is completed, either a reception
completion interrupt (INTSRn) or a reception error interrupt (INTSREn) is generated according to the ISRM
bit setting in the ASIMn register.
If the RXEn bit is reset (0) during a receive operation, the receive operation is immediately stopped. The
contents of receive buffer register n (RXBn) and of the asynchronous serial interface status register
(ASISn) at this time do not change, and no reception completion interrupt (INTSRn) or reception error
interrupt (INTSREn) is generated.
No reception completion interrupt is generated when RXEn = 0 (reception is disabled).
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
User’s Manual U15905EJ2V1UD
When the receive operation begins, serial data is stored