UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 450

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.5 Software Exception
acknowledged.
17.5.1 Operation
routine.
becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.
448
A software exception is generated when the CPU executes the TRAP instruction, and can always be
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the EP and ID bits of the PSW.
<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC,
The following illustrates the processing of a software exception.
The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 0 to 0FH, it
Note TRAP instruction format: TRAP vector (the vector is a value from 0 to 1FH.)
and transfers control.
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
CPU processing
Figure 17-8. Software Exception Processing
User’s Manual U15905EJ2V1UD
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Exception processing
TRAP instruction
Restored PC
PSW
Exception code
1
1
Handler address
Note